1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a circuit and method for selecting a word line of a semiconductor memory apparatus in a refresh mode.
2. Related Art
In semiconductor memory apparatuses, memory cells for recording data are classified into various units in order to easily control the data.
For example, the memory cells are grouped into banks. The banks are then grouped into mats.
Numerous word lines for recording or reading data on or from the cells are formed in a row direction in the bank.
For example, as shown in FIG. 1, when the banks are divided into a mat A and a mat B, the word lines are divided into word lines WL_MA<0:N> corresponding to the mat A and word lines WL_MB<0:N> corresponding to the mat B.
In a dynamic random access memory (DRAM), which is the most popular non-volatile memory, data loss occurs in the cells having data recorded thereon after a predetermined time has elapsed. Therefore, the semiconductor memory apparatus should perform a refresh operation for recording data recorded on the cells at the original data level again in order to prevent the cell data loss. The refresh operation is divided into two main refresh operations, that is, a self refresh operation in which the semiconductor memory apparatus performs a refresh operation at a predetermined time interval, and an auto refresh operation in which the semiconductor memory apparatus performs a refresh operation according to a refresh command input from the outside.
Before the refresh operation, an operation for selecting the word lines in a predetermined order should be performed. When the word line is selected, a refresh operation is performed on the cell connected to the selected word line. The semiconductor memory apparatus is provided with a word line selecting circuit for selecting the word line.
Next, the word line selecting circuit of the semiconductor memory apparatus according to the related art will be described below.
As shown in FIG. 2, the word line selecting circuit of the semiconductor memory apparatus according to the related art includes: a decoder 20 that decodes an input address A<0:n> and selects a word line corresponding to the decoded results from a plurality of word lines WL_MA<0:N> and WL_MB<0:N>; and an address counter 10 that counts the address A<0:n> using a refresh pulse REFP. The refresh pulse is generated in a refresh period according to a self refresh command or an auto refresh command.
As shown in FIG. 3, the address counter 10 includes a plurality of counters CNT0 to CNTn that are connected in series to each other to count the address A<0:n>. A self refresh signal SREF in addition to an output signal of a previous counter is input to the counter CNTn for counting the most significant bit address An.
The counter CNT0 receives the refresh pulse REFP and counts an address A0, and each of the counters CNT1 to CNTn receives an output signal of a previous counter and counts the corresponding address A<1:n>.
In the self refresh operation, two word lines of the mats A and B shown in FIG. 1 are simultaneously selected in order to reduce current consumption, and the cells connected to the selected word lines are refreshed. In this case, the counter CNT1 to CNTn−1 operates normally to count the address A<0:n−1>, and then output the counted address. The output of the counter CNTn is cut off by the self refresh signal SREF. A separate structure (not shown) generates the most significant address An to be output from the counter CNTn and simultaneously selects two word lines of the mats A and B.
Meanwhile, in the auto refresh operation, the word line of the mat A and the word line of the mat B shown in FIG. 1 are sequentially selected, and the cells connected to the selected word lines are refreshed. For example, assuming that word lines WL_MA<0:3> and WL_MB<0:3> are provided and addresses for selecting the word lines are A<0:2>, as shown in FIG. 4, the address A<0:2> increases in the order of 000, 001, 100, 101, 010, 011, 110, and 111, and the word lines WL_MA<0>, WL_MB<0>, WL_MA<1>, WL_MB<1>, WL_MA<2>, WL_MB<2>, WL_MA<3>, and WL_MB<3> are selected.
However, the word line selecting circuit of the semiconductor memory apparatus according to the related art sequentially selects word lines and performs refresh during the auto refresh operation, which may cause cell data loss. For example, according to the self refresh operation, when an auto refresh command is input immediately after pairs of word lines WL_MA<0> and WL_MB<0>, WL_MA<1> and WL_MB<1>, and WL_MA<2> and WL_MB<2> shown in FIG. 1 are selected and then refresh is performed, the word lines are selected in the order of WL_MA<3>, WL_MA<4>, WL_MA<5>, . . . , WL_MA<N>, WL_MB<1>, WL_MB<2>, . . . , WL_MB<N>, and then refresh is performed. Therefore, the word lines after the word line WL_MB<2> are refreshed at a time later than that at which the other word lines are refreshed, which may cause cell data loss.